// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  glb_cfg_vclk_reg_offset_field.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:42 Create file
// ******************************************************************************

#ifndef __GLB_CFG_VCLK_REG_OFFSET_FIELD_H__
#define __GLB_CFG_VCLK_REG_OFFSET_FIELD_H__

#define GLB_CFG_VCLK_TEST_RESERVE0_LEN    31
#define GLB_CFG_VCLK_TEST_RESERVE0_OFFSET 1
#define GLB_CFG_VCLK_IS_AVSPLUS_LEN       1
#define GLB_CFG_VCLK_IS_AVSPLUS_OFFSET    0

#define GLB_CFG_VCLK_ACFG2ARB_REPEAT_CNT_LEN    4
#define GLB_CFG_VCLK_ACFG2ARB_REPEAT_CNT_OFFSET 12
#define GLB_CFG_VCLK_ACFG2ARB_RAMTYPE_LEN       2
#define GLB_CFG_VCLK_ACFG2ARB_RAMTYPE_OFFSET    8
#define GLB_CFG_VCLK_AXI_4K_BYPASS_LEN          1
#define GLB_CFG_VCLK_AXI_4K_BYPASS_OFFSET       4
#define GLB_CFG_VCLK_AXI_SEP_TYP_LEN            2
#define GLB_CFG_VCLK_AXI_SEP_TYP_OFFSET         0

#define GLB_CFG_VCLK_TEST_RESERVE1_LEN    30
#define GLB_CFG_VCLK_TEST_RESERVE1_OFFSET 2
#define GLB_CFG_VCLK_DEBUG_EN_LEN         1
#define GLB_CFG_VCLK_DEBUG_EN_OFFSET      1
#define GLB_CFG_VCLK_RSTSELF_OR_NO_LEN    1
#define GLB_CFG_VCLK_RSTSELF_OR_NO_OFFSET 0

#define GLB_CFG_VCLK_MEMROY_CLOCK_GATING_EN_TMP_LEN    1
#define GLB_CFG_VCLK_MEMROY_CLOCK_GATING_EN_TMP_OFFSET 1
#define GLB_CFG_VCLK_MODULE_CLOCK_GATING_EN_LEN        1
#define GLB_CFG_VCLK_MODULE_CLOCK_GATING_EN_OFFSET     0

#define GLB_CFG_VCLK_VDH_USE_STATE_LEN    32
#define GLB_CFG_VCLK_VDH_USE_STATE_OFFSET 0

#define GLB_CFG_VCLK_OVER_TIME_LEN    32
#define GLB_CFG_VCLK_OVER_TIME_OFFSET 0

#define GLB_CFG_VCLK_CFG_ARQOS_FLAG_LEN        1
#define GLB_CFG_VCLK_CFG_ARQOS_FLAG_OFFSET     12
#define GLB_CFG_VCLK_CFG_PRC_HEAD_ARQOS_LEN    3
#define GLB_CFG_VCLK_CFG_PRC_HEAD_ARQOS_OFFSET 8
#define GLB_CFG_VCLK_CFG_PRC_DATA_ARQOS_LEN    3
#define GLB_CFG_VCLK_CFG_PRC_DATA_ARQOS_OFFSET 4
#define GLB_CFG_VCLK_CFG_DEFAULT_ARQOS_LEN     3
#define GLB_CFG_VCLK_CFG_DEFAULT_ARQOS_OFFSET  0

#define GLB_CFG_VCLK_VDH_ARQOS_CYCLE_LEN    32
#define GLB_CFG_VCLK_VDH_ARQOS_CYCLE_OFFSET 0

#define GLB_CFG_VCLK_VDH_ARQOS_NUMBERS_LEN    32
#define GLB_CFG_VCLK_VDH_ARQOS_NUMBERS_OFFSET 0

#define GLB_CFG_VCLK_ACFG2ARB_CH1_MAX_REPEAT_LEN    6
#define GLB_CFG_VCLK_ACFG2ARB_CH1_MAX_REPEAT_OFFSET 8
#define GLB_CFG_VCLK_ACFG2ARB_CH0_MAX_REPEAT_LEN    6
#define GLB_CFG_VCLK_ACFG2ARB_CH0_MAX_REPEAT_OFFSET 0

#define GLB_CFG_VCLK_SCD_FORCE_REQ_ACK_LEN     1
#define GLB_CFG_VCLK_SCD_FORCE_REQ_ACK_OFFSET  1
#define GLB_CFG_VCLK_MFDE_FORCE_REQ_ACK_LEN    1
#define GLB_CFG_VCLK_MFDE_FORCE_REQ_ACK_OFFSET 0

#define GLB_CFG_VCLK_MEM_CTRL_RFS_LEN    32
#define GLB_CFG_VCLK_MEM_CTRL_RFS_OFFSET 0

#define GLB_CFG_VCLK_MEM_CTRL_RFT_LEN    32
#define GLB_CFG_VCLK_MEM_CTRL_RFT_OFFSET 0

#define GLB_CFG_VCLK_MEM_CTRL_ROM_LEN    32
#define GLB_CFG_VCLK_MEM_CTRL_ROM_OFFSET 0

#define GLB_CFG_VCLK_ECC_BYPASS_LEN            1
#define GLB_CFG_VCLK_ECC_BYPASS_OFFSET         1
#define GLB_CFG_VCLK_MEM_ERR_CHECK_FLAG_LEN    1
#define GLB_CFG_VCLK_MEM_ERR_CHECK_FLAG_OFFSET 0

#endif // __GLB_CFG_VCLK_REG_OFFSET_FIELD_H__
